FIELD OF THE INVENTION
The invention relates to a memory cell having the following features:
a semiconducting base body with a first main surface, PA1 a first doped region of a first conduction type on the first main surface, the first doped region connected to a drain terminal, PA1 a second doped region of the first conduction type on the first main surface, the second doped region connected to a source terminal, PA1 a floating gate layer disposed on the first main surface, having an oxide layer underneath it, covering a region between the first and second doped regions and partially covering at least one of the two doped regions, and PA1 a control gate layer disposed on the floating gate layer, having a dielectric underneath it and connected to a control gate terminal. The invention also relates to a method for producing the memory cell.
Such a memory cell is disclosed, for example, in the book entitled "Lehrbuch der Hochfrequenztechnik" [Textbook of Radio-Frequency Technology] by Meinke and Gundlach, Springer, 5th Edition, 1992, page M 40 et seq. In memory cells of that type, the flow of current between the two doped regions, which are respectively connected to the gate terminal and the source terminal, is critically influenced by a charge situated in the floating gate layer.
The floating gate layer can be charged and/or discharged, utilizing the Fowler-Nordheim tunnel effect, for example, by the flow of a tunneling current between the floating gate layer and one of the two doped regions. Following conventions in the literature, it is assumed in the following text that the first doped region, which is connected to the drain terminal and is frequently also referred to as the drain region, is the doped region from which the tunneling current commences toward the floating gate, but that does not preclude the possibility of a tunneling current also flowing between the floating gate layer and the second doped region, which is connected to the source terminal, instead of the drain region.
The commencement of a tunneling current between the floating gate layer and the drain region necessitates not only the application of a sufficiently high voltage between the control gate terminal and the drain terminal but also overlapping of the floating gate layer over the drain region. In that case, the level of the voltage to be applied, which is also referred to as the programming voltage, and the required duration for charging the floating gate layer from a lower potential, to an upper potential, and discharging it from an upper potential to a lower potential, which is also referred to as the programming time, are sensitively dependent on the overlap region.
In the case of previous memory cells, a common structure edge of the control gate layer and the floating gate layer, which is also referred to as the gate edge, is usually provided over the drain region, that is to say the control gate layer and the floating gate layer cover the drain region to the same extent. For that reason, during the process of producing such memory cells, on the first main surface of the base body, the drain region can be doped into the first main surface only as far as the gate edge, with the result that an overlap region of the floating gate layer and drain region does not yet exist. The overlap region is produced from subsequent thermal diffusion of the drain region under the floating gate layer, with that overlap region being restricted, inter alia, by three circumstances:
1. For various reasons, the drain region may not be doped as far as the gate edge, which results in a smaller overlap region during the subsequent diffusion.
2. In the course of oxidations which follow during production, a thicker oxide layer, a so-called bird's beak, is formed on the gate edge, as a result of which the tunneling current density is exponentially reduced.
3. The dopant concentration greatly decreases in the lateral direction, with the result that efficient tunneling of the charge carriers can only take place at the gate edge.
Overall, then, small process fluctuations during the production of the memory cells described to date can lead to a large variation in the programming voltage and programming time, since that region of the overlap region of the drain region and the floating gate layer which is critical for tunneling is given by the difference between the length of the bird's beak and the length of the doped region which is diffused under the floating gate layer, and cannot be exactly defined.